Encoding:

Format:

ADDQH[_R].W 

ADDQH.W     rd, rs, rt

ADDQH_R.W   rd, rs, rt

Purpose:

Add Fractional Words And Shift Right to Halve Results

Fractional addition of word vectors, with a right shift by one bit to halve the result, with optional rounding.

Description:

rd = sign_extend(round((rs31..0 + rt31..0) >> 1))

The right-most word in register rs is added to the right-most word in register rt to create an interim 33-bit result.

In the non-rounding instruction variant, the interim result is then shifted right by one bit before being written to the destination register rd.

In the rounding version of the i nstruction, a value of 1 is added at the least-significant bit position of the interim result; the interim result is then right-shifted by one bit and written to the destination register.

This instruction does not modify the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

ADDQH.W:
   tempA31..0 = rightShift1AddQ32( GPR[rs]31..0 , GPR[rt]31..0 )
   GPR[rd]63..0 = (tempB15)32 || tempA31..0
ADDQH_R.W:
   tempA31..0 = roundRightShift1AddQ32( GPR[rs]31..0 , GPR[rt]31..0 )
   GPR[rd]63..0 = (tempB15)32 || tempA31..0
function rightShift1AddQ32( a31..0 , b31..0 )
   temp32..0 = (( a31 || a31..0 ) + ( b31 || b31..0 ))
   return temp32..1
endfunction rightShift1AddQ32
function roundRightShift1AddQ32( a31..0 , b31..0 )
   temp32..0 = (( a31 || a31..0 ) + ( b31 || b31..0 ))
   temp32..0 = temp32..0 + 1
   return temp32..1
endfunction roundRightShift1AddQ32

Exceptions:

Reserved Instruction, DSP Disabled